This application is related to Japanese application No. HEI 10(1998)-325252 filed on Nov. 16, 1998, whose priority is claimed under 35 USC xc2xa7119, the disclosure of which is incorporated by reference in its entirety.
1. Field of the Invention
The present invention relates to a semiconductor device and a process for manufacturing the same. More particularly, the invention relates to a process for forming a device isolation region in an integrated circuit device.
2. Description of Related Art
With high integration of integrated circuit devices, miniaturization of device isolation regions as well as devices themselves is in progress. Recently, device isolation techniques using trenches are under development in place of conventionally utilized LOCOS methos.
In the trench isolation techniques, a trench is formed on the surface of a silicon substrate, an insulating film is formed on the silicon substrate including the trench and the insulating film is polished by a chemical mechanical polishing (CMP) method or the like, thereby to flatten the surface with the insulating film buried in the trench.
However, such techniques have a so-called dishing problem that, in the case where an insulating film buried in a wide trench is polished, the insulating film is polished faster in the central portion of the trench and the insulating film becomes thin there.
There is also a so-called erosion problem that, in an active region surrounded by wide trenches (of several xcexcm width, for example), the polishing of the active region progresses excessively and therefore the surface of the silicon substrate is polished.
To cope with these problems, for example, Japanese Unexamined Patent Publication No. HEI 9(1997)-181159 proposes a method for avoiding dishing and erosion about trenches by forming a dummy pattern of regularly repeated trenches.
This method is described with reference to FIGS. 5(a) to 5(f).
First, as shown in FIG. 5(a), a pad oxide film 202 is formed on a silicon substrate 201 by a thermal oxidization method and a silicon nitride film 203 is formed by a reduced-pressure CVD method. Subsequently, a pattern of resist films 204a to 204i is formed by a photolithography process using a mask which defines an active region.
Subsequently, as shown in FIG. 5(b), the silicon nitride film 203 and the pad oxide film 202 are selectively etched sequentially using the resist pattern 204a to 204i as an etching mask. Further, the silicon substrate is etched anisotropically etched to form trenches 205a to 205h having a depth of about 0.3 xcexcm to about 0.6 xcexcm. Thereafter, the resist pattern 204a to 204i is removed by ashing. At this time, narrow device isolation regions such as 205a and 205b are each composed only of a single narrow trench, while wide device isolation regions, 206a and 206b, are composed of trenches 205c, 205d and 205e and pseudo active regions 204d and 204e, and of trenches 205f, 205g and 205h and pseudo active regions 204g and 204h, respectively.
Subsequently, a silicon oxide film 207 is formed on the resulting silicon substrate 201 by a CVD method and polished by a CMP method to expose the surface of the silicon nitride film 203. Then the silicon nitride film 203 and the pad oxide film 202 are removed with a heated phosphoric acid solution and a diluted hydrofluoric acid solution, respectively. Thereafter, impurities are implanted for forming a well (not shown). Further, as shown in FIG. 5(c), the surface of the resulting silicon substrate 201 is oxidized to form a gate oxide film 208.
Thereafter, as shown in FIG. 5(d), a gate electrode 209, source/drain regions 211 and an interconnect 210 are formed by conventional techniques. The interconnect 210 is formed on the trench 205d sandwiched by the pseudo active regions 204d and 204e, and the width thereof is smaller than that of the trench 205d. 
Next, as shown in FIG. 5(e), a resist used as a mask (not shown) for the impurity implantation is removed according to a conventional process. Thereafter, a thermal treatment is conducted to activate the implanted impurities. Further, a salicide such as TiSi2 is formed as required on the surface of the active region and an interlayer dielectric film 212 is formed on the entire surface of the resulting silicon substrate 201.
Subsequently, as shown in FIG. 5(f), the surface of the interlayer dielectric film 212 is polished and flattened by a CMP method.
According to the above-described method, the dishing and erosion about trenches can be prevented. However, there still remains a problem of dishing in the interlayer dielectric film that, when the interlayer dielectric film 212 is flattened by the CMP method after its deposition, a sparse portion where interconnects do not exist is polished much faster than a dense portion. Such level difference in the interlayer dielectric film generated by varying density of interconnects decreases the depth of focus in later lithography processes for forming contact holes and a wiring layer, and produces variations in the depth of the contact holes. That makes difficult the etching process for forming the contact holes and also impedes the miniaturization of devices.
The present invention provides a semiconductor device comprising: a semiconductor substrate; a plurality of active regions for forming semiconductor elements, the active regions being formed on the semiconductor substrate; a device isolation region for separating the plural active regions from each other, the device isolation region including a trench region filled with an insulating film and a pseudo active region formed adjacent to the trench region; a wiring layer formed above the semiconductor substrate; and a pseudo conductive film formed on the device isolation region, wherein, if the pseudo conductive film is partially or entirely located under the wiring layer, the pseudo conductive film is formed only on the trench region.
In another aspect, the present invention provides a process for manufacturing a semiconductor device including: a semiconductor substrate of a first conductive type; a plurality of active regions for forming a MOS transistor provided with a gate insulating film, a gate electrode and source/drain regions, the active regions being formed on the semiconductor substrate; a device isolation region for separating the plural active regions from each other, the device isolation region including a trench region filled with an insulating film, and a pseudo active region formed adjacent to the trench region and having a diffusion layer of a second conductivity type on the surface thereof; a wiring layer formed above the semiconductor substrate; and a pseudo conductive film formed on the device isolation region, which is formed only on the trench region if the pseudo conductive film is partially or entirely located under the wiring layer, which process comprises the step of forming the diffusion layer of the second conductivity type on the surface of the pseudo active region simultaneously when the source/drain regions are formed, or which process comprises the step of forming the pseudo conductive film on the device isolation region simultaneously when the gate electrode is formed.
These and other objects of the present application will become more readily apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.